Integrated circuits include various components that operate in different logic domains. These logic domains may include a complementary metal-oxide-semiconductor (CMOS) domain and a current mode logic (CML) domain. Often times, signals operating in one logic domain may be passed on to components operating in a different logic domain. Timing differences between signals operating in one logic domain may lead the introduction of unwanted noise when those signals are passed to a component operating in a different logic domain.
Differential signals generated in the CMOS domain are not generated from the same source, whereas differential signals generated in the CML domain are generated from the same source. Differential signals generated in the CMOS domain are two signals that are the inverse of each other, but do not originate from the same source. As such, these differential signals generated in the CMOS domain suffer from timing mismatches that result in a common mode signal that includes noise. Additionally, the signal swing in the CMOS domain is greater than that in the CML domain. Thus, if the inverted CMOS signals are directly connected to a component operating in the CML domain, a higher input signal swing is provided to the component operating in the CML domain than necessary. This in turn will lead to a greater amount of common mode noise being injected into the power supply of the component operating in the CML domain than desirable.